1. Field of the Invention
The present invention relates to a direct memory access controller (DMAC), and more particularly, to a method and apparatus for controlling direct memory access to prevent a decrease in system performance by minimizing generation of interrupts.
This work was supported by the IT R&D program of MIC/IITA [2005-S-100-02, Development of Multi-codec and Its Control Technology Providing Variable Bandwidth Scalability]
2. Description of the Related Art
In general, voice data are processed on a ten to twenty millisecond basis in a voice over Internet protocol (VoIP) phone system. For this, a voice output unit of the VoIP phone system can include a high-capacity output storage medium such as a high-capacity first input first output (FIFO) for outputting voice data on a ten to twenty millisecond basis at a time. However, in this case, the manufacturing costs and size of the VoIP phone system increase due to the high-capacity output storage medium.
For this reason, VoIP phone systems use a low-capacity output storage medium and output voice data discretely.
Meanwhile, a voice output unit of a VoIP phone system receives voice data using a direct memory access controller (DMAC) in order to minimize intervention of a processor.
In response to a DMAC operation request sent from the voice output unit, the DMAC reads a portion of voice data corresponding to a burst size of an output storage medium from an external memory and transmits the read portion of the voice data to the voice output unit. Then, the DMAC generates an interrupt signal to inform a processor that the portion of the voice data is completely transmitted.
When the processor receives the interrupt signal, the processor suspends its current operation and stores information about the suspended operation in a memory such as the external memory. Then, the processor processes the interrupt signal prior to others and reads the information about the suspended operation from the external memory to resume the suspended operation.
However, it takes much more time for the processor to access the external memory for performing the above-described operation as compared with the time required for the processor to perform its internal operation. Therefore, system performance steeply decreases as the processor accesses the external memory more frequently for processing interrupt signals.
In other words, the system performance decreases much more when the DMAC generates more interrupt signals.